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Author:

姚丹 (姚丹.) | 林平分 (林平分.) | 楼煌 (楼煌.)

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CQVIP

Abstract:

基于原型验证的需要和FPGA对ASIC市场的取代,越来越多 ASIC设计需要移植到FPGA上来实现.然而,ASIC与FPGA在内部结构上差异很大,尤其是时钟结构,在移植过程中需要特别注意.文中以Xilinx公司的Vitrex--4FPGA为例,对比了ASIC与FPGA的时钟结构,给出了门控时钟、生成时钟和多FPGA时钟同步在设计转换过程中的处理方法.

Keyword:

生成时钟 ASIC 门控时钟 FPGA

Author Community:

  • [ 1 ] [姚丹]北京工业大学
  • [ 2 ] [林平分]北京工业大学
  • [ 3 ] [楼煌]北京工业大学

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Source :

电子元器件应用

ISSN: 1563-4795

Year: 2008

Issue: 7

Volume: 10

Page: 43-47

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count: 11

Chinese Cited Count:

30 Days PV: 1

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