Formal　check　provides　a　method　for　detecting　problems　of　SoC　design　in　early　time　of　verification.　Looking　at　SoC　design　issues,　most　of　design　integration　errors　come　from　modules　connectivity.　Combining　above　two　points,　this　paper　descripts　an　approach　check　signal　connectivity　with　formal　check　method.　The　approach　parses　Verilog　HDL　RTL　code　through　a　program,　which　writes　by　script　language　Perl,　to　analysis　signals　connectivity.　It＇s　helpful　for　both　SoC　designer　and　verification　engineer.