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Author:

Zhao, Jun (Zhao, Jun.) | Peng, Xiao-Hong (Peng, Xiao-Hong.) | Hou, Li-Gang (Hou, Li-Gang.) | Zhang, Yi-Nan (Zhang, Yi-Nan.) | Sun, Guo-Qing (Sun, Guo-Qing.)

Indexed by:

CPCI-S

Abstract:

A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35 mu m CMOS technology with low power low temperature-coefficient( TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/degrees C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42 mu A and start-up time is 2.04 mu s.

Keyword:

BGR Curvature-Compensated high PSRR low power low TC

Author Community:

  • [ 1 ] [Zhao, Jun]Beijing Univ Technol, VLSI & Syst Lab, Beijing, Peoples R China
  • [ 2 ] [Peng, Xiao-Hong]Beijing Univ Technol, VLSI & Syst Lab, Beijing, Peoples R China
  • [ 3 ] [Hou, Li-Gang]Beijing Univ Technol, VLSI & Syst Lab, Beijing, Peoples R China
  • [ 4 ] [Zhang, Yi-Nan]Beijing Univ Technol, VLSI & Syst Lab, Beijing, Peoples R China
  • [ 5 ] [Sun, Guo-Qing]Beijing Univ Technol, VLSI & Syst Lab, Beijing, Peoples R China

Reprint Author's Address:

  • [Peng, Xiao-Hong]Beijing Univ Technol, VLSI & Syst Lab, Beijing, Peoples R China

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Source :

2017 2ND IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM)

Year: 2017

Page: 191-194

Language: English

Cited Count:

WoS CC Cited Count: 8

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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