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Author:

SunJianhui (SunJianhui.) | Wanggongtang (Wanggongtang.) | Huaqing (Huaqing.) | Wangchunxing (Wangchunxing.) | Wanjinfeng (Wanjinfeng.) | Liujuntao (Liujuntao.) | Caixinxia (Caixinxia.) | Houligang (Houligang.)

Indexed by:

CPCI-S

Abstract:

In this paper, an intelligent and low power EEG(electroencephalograph) processing multi-QOS(quality of service) DSP has been designed with the smicrf180nm technology used for EEG wearable Instrument. The bio-detection uses the Ag/Ag-Cl electrode sensor to extract the head skin's micro EEG signal, and uses the differential chopper-LNA circuit to cancel the 1/f, dc-offset voltage and other noises. On one hand, the hardware accelerator uses the STFT(short time fourier transform) multiple filtering channels and the HT(hilbert transform) method, for decomposing the instant amplitude envelop and instant frequency of each sub-channel. On the other hand, when the detected SI(sleepiness indicator) signal triggers the minimum 3-stage CPU, the software thread uses the HHT(hilbert huang transform) method to get the IMF(intrinsic mode function) components from the non-statistical and non-stable EEG signal, then the design executes the Tsallis entropy complexity analysis with the pipeline CPU, which consumes about 20pJ/instruction. The transmitter uses ping/pang switching matrix, the burst TD-OFDM (time division-orthogonal frequency division multiplex) scheme and the power-adaptation algorithm to give a balance design between the frequency utility and the energy consumption. To increase the throughput and to decrease power consumption mostly caused by the wireless channel's idle CS (carrier sensing) operation, the channel wake-upping/monitoring and the data transmitting/receiving circuits are separated, which reduces the energy consumption by about 30x The design uses one-hop star topology to compose the reduced network architecture. Also, the design mainly uses the CG (clock gating) and PG (power gating) methods to decrease the chip's dynamic and leakage energy consumption respectively.

Keyword:

hardware accelerator smart SOC low power FFG monitoring

Author Community:

  • [ 1 ] [SunJianhui]Shandong Normal Univ, Coll Phys & Elect, Jinan, Shandong, Peoples R China
  • [ 2 ] [Wanggongtang]Shandong Normal Univ, Coll Phys & Elect, Jinan, Shandong, Peoples R China
  • [ 3 ] [Huaqing]Shandong Normal Univ, Coll Phys & Elect, Jinan, Shandong, Peoples R China
  • [ 4 ] [Wangchunxing]Shandong Normal Univ, Coll Phys & Elect, Jinan, Shandong, Peoples R China
  • [ 5 ] [Wanjinfeng]Shandong Normal Univ, Coll Phys & Elect, Jinan, Shandong, Peoples R China
  • [ 6 ] [SunJianhui]Chinese Acad Sci Univ, Beijing, Peoples R China
  • [ 7 ] [Liujuntao]Chinese Acad Sci Univ, Beijing, Peoples R China
  • [ 8 ] [Caixinxia]Chinese Acad Sci Univ, Beijing, Peoples R China
  • [ 9 ] [Houligang]Beijing Univ Technol, Coll Microelect, Beijing, Peoples R China

Reprint Author's Address:

  • [SunJianhui]Shandong Normal Univ, Coll Phys & Elect, Jinan, Shandong, Peoples R China;;[SunJianhui]Chinese Acad Sci Univ, Beijing, Peoples R China

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Source :

2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)

Year: 2016

Page: 210-214

Language: English

Cited Count:

WoS CC Cited Count: 1

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 0

Affiliated Colleges:

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