This　paper　presents　a　more　complex　algorithm　with　Verilog-HDL,　which　based　on　the　dual-modulus　preseted　decimal　frequency　divider.　This　algorithm　can　not　only　increase　the　accuracy　of　decimal　frequency　divider.,　but　also　can　be　used　to　divide　a　clock.　Simulations　are　conducted　to　analyze　the　characteristics　of　the　decimal　frequency　divider　and　DDS　divider.　The　results　shows　that　the　divider　can　satisfy　the　requirements　of　design.