A　model　for　analyzing　and　optimizing　the　active　power,　the　leakage　power　and　the　delay　of　the　domino　OR　gates　with　the　sleep　transistor　based　on　wavelet　neural　networks　in　45　nm　CMOS　technology　is　proposed.　By　studying　the　impact　of　the　sleep　transistor,　the　model　can　successfully　forecast　the　nonlinear　changing　of　the　active　power,　the　leakage　power　and　the　delay　of　the　different　inputs　domino　OR　gates.　The　simulation　results　for　verification　indicate　that　the　forecasting　model　can　be　well　applied　in　VLSI　design　with　accuracy　ratio　of　more　than　90%(1).