The　gate　reliability　of　Hf0.5Zr0.5O2　(HZO)　ferroelectric　field-effect　transistors　(FeFETs)　with　varying　interface　layers　was　investigated　in　this　paper,　specifically　SiO2　and　Y2O3.　By　employing　voltage-ramp　and　time-dependent　dielectric　breakdown　(TDDB)　tests,　along　with　an　analysis　of　different　gate　dimensions,　we　provide　insights　into　the　impact　of　interface　layer　composition　and　device　geometry　on　FeFET　performance　and　reliability　in　this　study.　The　research　aims　to　enhance　device　longevity　and　efficiency　by　understanding　and　optimizing　the　interface　layer＇s　dielectric　properties,　addressing　the　critical　challenge　of　gate　dielectric　failure,　and　guiding　future　design　strategies　for　improved　ferroelectric　memory　devices.　©　Published　under　licence　by　IOP　Publishing　Ltd.