A　low　power　processor　(LPP)　for　wireless　sensor　network　(WSN)　is　implemented,　based　on　90nm　technology.　In　order　to　reduce　power　consumption,　two　methods　are　selected　in　the　design.　Clock　gating　technique　is　used　to　reduce　the　dynamic　power　dissipations,　and　multiple　threshold　voltage　library　is　adopted　to　depress　leakage　power　consumption.　This　paper　reports　the　design　results　with　a　brief　discussion.