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Abstract：
Comparing two finite state machines, how to use VHDL to design a reliable and stable finite state machine is declared. Due to the difference between the two finite state machines, then their stability is different with new method proposed in this paper, we can design a reliable and stable finite state machine when take normal code method.
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Journal of Beijing University of Technology
ISSN： 0254-0037
Year： 2005
Issue： 1
Volume： 31
Page： 21-24
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ESI Highly Cited Papers on the List： 0 Unfold All
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30 Days PV： 0
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