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Author:

Qiuyun, Xu (Qiuyun, Xu.) | Ligang, Hou (Ligang, Hou.) | Qiming, Luo (Qiming, Luo.) | Jinhui, Wang (Jinhui, Wang.) | Shuqin, Geng (Shuqin, Geng.)

Indexed by:

EI Scopus

Abstract:

In this paper, UVM (Universal Verification Methodology) is adopted to build the SHA-256 IP verification platform. The generic code of the verification platform is automatically generated by the Perl script. That is the semi-automatic UVM platform. It forms the verification structure of the module level and the top level. Based on the platform, the remaining of the core code is added to the testbench. Then according to the verification scheme, a large number of test cases produce the stimulus to the DUT, which make the functional coverage achieve 100%, the code coverage and the waveform meet the requirements. The results show the SHA-256 IP design successfully and the semi-automatic UVM platform is usable. © 2017 IEEE.

Keyword:

Verification Design for testability Automation

Author Community:

  • [ 1 ] [Qiuyun, Xu]VLSI and System Lab, Beijing University of Technology, Beijing; 10024, China
  • [ 2 ] [Ligang, Hou]VLSI and System Lab, Beijing University of Technology, Beijing; 10024, China
  • [ 3 ] [Qiming, Luo]VLSI and System Lab, Beijing University of Technology, Beijing; 10024, China
  • [ 4 ] [Jinhui, Wang]Department of Electrical and Computer Engineering, North Dakota State University, ND; 58102, United States
  • [ 5 ] [Shuqin, Geng]VLSI and System Lab, Beijing University of Technology, Beijing; 10024, China

Reprint Author's Address:

  • [ligang, hou]vlsi and system lab, beijing university of technology, beijing; 10024, china

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Source :

Year: 2017

Volume: 2018-January

Page: 111-115

Language: English

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 4

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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