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Author:

Wang, J. (Wang, J..) | Gong, N. (Gong, N..) | Peng, X. (Peng, X..) | Hou, L. (Hou, L..) | Geng, S. (Geng, S..) | Wu, W. (Wu, W..)

Indexed by:

Scopus

Abstract:

Using Wavelet Neural Networks (WNN), low power domino circuit performance statistical characterization is investigated in this paper. The proposed model successfully estimates the nonlinear changing of the leakage power, the active power, and the delay of the different fanin low power domino gates with the dual threshold voltage technique (DVT), the multiplesupply technique (MST), and the sleep transistor technique (SST). At last, the precision priority of estimating system is obtained, and process and temperature variationeffect on estimation errors is analyzed. © 2011 International Information Institute.

Keyword:

Delay; Domino circuits; Low power; Neural networks

Author Community:

  • [ 1 ] [Wang, J.]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 2 ] [Gong, N.]Department of Computer Science and Engineering, SUNY at Buffalo, Buffalo, NY 14260, United States
  • [ 3 ] [Peng, X.]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 4 ] [Hou, L.]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 5 ] [Geng, S.]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 6 ] [Wu, W.]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China

Reprint Author's Address:

  • [Wang, J.]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China

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Information

ISSN: 1343-4500

Year: 2011

Issue: 3

Volume: 14

Page: 803-809

Language: English

JCR Journal Grade:4

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 2

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