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学者姓名：秦飞
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Abstract ：
The 2.5-D package is intended to deliver increased input/output (IO) density and high-frequency electrical performance while meeting cost requirements. It achieves chip heterogeneous integration capabilities through the interposer. However, some warpage will always occur during the molding process because of the different coefficients of thermal expansion between the chip and the molding compound. One of the challenges is predicting and controlling wafer warpage. This article focuses on wafer warpage prediction and optimization of the through glass via (TGV) interposer. The plate and shell bending theory and the composite material equivalence method are introduced in the discussion of the wafer warpage problem. A set of wafer-level warpage theoretical calculation models is proposed, and the calculation accuracy of the warpage theoretical model is verified by the finite-element simulation and experiment. Meanwhile, its actual engineering application is given to provide direction for the design of wafer-level packaging products for TGV interposer.
Keyword ：
Glass Glass Semiconductor device modeling Semiconductor device modeling Manufacturing Manufacturing Substrates Substrates through glass via (TGV) through glass via (TGV) Bending Bending glass interposer glass interposer plate and shell bending theory plate and shell bending theory Packaging Packaging warpage prediction warpage prediction Finite-element modeling (FEM) Finite-element modeling (FEM) Residual stresses Residual stresses
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| GB/T 7714 | Zhao, Jin , Qin, Fei , Yu, Daquan . Warpage Prediction and Optimization for Wafer-Level Glass Interposer Packaging [J]. | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2024 , 14 (8) : 1394-1402 . |
| MLA | Zhao, Jin 等. "Warpage Prediction and Optimization for Wafer-Level Glass Interposer Packaging" . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 14 . 8 (2024) : 1394-1402 . |
| APA | Zhao, Jin , Qin, Fei , Yu, Daquan . Warpage Prediction and Optimization for Wafer-Level Glass Interposer Packaging . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2024 , 14 (8) , 1394-1402 . |
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Abstract ：
MOSFETs offer a number of benefits relative to traditional power devices. These include a higher switching frequency, higher operating temperature, and higher breakdown voltage. As a result, there has been considerable interest in these devices within the industry. However, alongside this interest, it has become clear that the reliability of MOSFETs is becoming increasingly significant in the research domain. This is because MOSFETs are used in a wide variety of applications in a range of different fields. One of the most significant causes of failure in MOSFET modules is solder layer degradation, which encompasses solder layer delamination and voids. This paper therefore investigates the impact of solder layer voids on the electrical and thermal characteristics of MOSFET modules. Firstly, a simplified finite element model is established, and an electro-thermal simulation analysis is carried out under power cycle conditions. Secondly, finite element models of different defective solder layers are established. The results of the simulations conducted using the aforementioned models are then compared and analyzed. The analysis reveals that the temperature on the chip rises in direct proportion to the increase in defect area, while the current density of the solder layer also increases significantly with the expansion of void area. This provides a certain reference point for the subsequent study of solder degradation.
Keyword ：
FEM FEM MOSFETs MOSFETs Solder layer Solder layer
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| GB/T 7714 | Zeng, Qiang , An, Tong , Qin, Fei et al. Research on the influence of solder layer defects on chip junction temperature [J]. | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
| MLA | Zeng, Qiang et al. "Research on the influence of solder layer defects on chip junction temperature" . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT (2024) . |
| APA | Zeng, Qiang , An, Tong , Qin, Fei , Wang, Yuxiang . Research on the influence of solder layer defects on chip junction temperature . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
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Abstract ：
In the field of electronic packaging structure reliability research, the Finite Element Method (FEM) is recognized as an effective and reliable approach for numerical simulation. Concurrently, the Boundary Element Method (BEM) is noted for its unique advantage of requiring discretization only at the boundary, which significantly reduces the degrees of freedom and potentially enhances the accuracy of analyses. This characteristic makes BEM particularly useful for analyzing multiscale structures in electronic packaging. Nevertheless, both methods have their limitations: FEM necessitates elements within the internal domain, making it computationally intensive, while BEM is most effective with linear problems and can be less versatile with nonlinear issues. Considering these factors, this paper introduces a FEM-BEM coupling algorithm designed to address the transient elastic dynamic response problem in electronic packaging structures. This approach is designed to leverage the strengths and mitigate the limitations of both the FEM and BEM. During the numerical simulation, the model is initially segmented into FE and BE domains. The FE domain is solved using ABAQUS, while the BE domain is analyzed through a self-written boundary element program. The BE domain functions as a specialized type of finite element, where its equivalent stiffness and load are determined by invoking the boundary element program via the User-Defined Element subroutine (UEL). These results are then integrated into the finite element system. Numerical examples demonstrate that the proposed FEMBEM coupling method is both effective and feasible for analyzing the dynamic response of electronic packaging structures.
Keyword ：
Electronic packaging Electronic packaging Elastic dynamics problems Elastic dynamics problems FEM-BEM coupling scheme FEM-BEM coupling scheme
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| GB/T 7714 | He, Yida , Gong, Yanpeng , Xu, Hao et al. A FEM-BEM coupling scheme for elastic dynamics problems in electronic packaging [J]. | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
| MLA | He, Yida et al. "A FEM-BEM coupling scheme for elastic dynamics problems in electronic packaging" . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT (2024) . |
| APA | He, Yida , Gong, Yanpeng , Xu, Hao , Qin, Fei . A FEM-BEM coupling scheme for elastic dynamics problems in electronic packaging . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
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Abstract ：
As a key component of power electronic devices, the reliability of insulated gate bipolar transistor (IGBT) modules has attracted widespread attention. Different structural parameters of Cu clips will have different effects on the parasitic inductance, on-resistance, and junction-shell thermal resistance of IGBT modules. Therefore, firstly, the finite element models of Cu clip structures with different structural parameters are established, and the parasitic inductance, on-resistance, and junction-shell thermal resistance of each simulation model are calculated through finite element simulation analysis. Secondly, the factorial method was used to study the effects of Cu clip size on parasitic inductance, on-resistance and junction-shell thermal resistance. Finally, the response surface method is used to optimize the structure design, and the prediction model of parasitic inductance, on-resistance and junction-shell thermal resistance is established, and the optimal combination design of parasitic inductance, on-resistance and junction-shell thermal resistance is obtained at the same time. The analysis results show that the thickness and width of the Cu clip have a greater influence on the parasitic inductance than the thickness. As the contact area between the Cu clip and the chip increases, the on-resistance and junction-shell thermal resistance decrease.
Keyword ：
insulated-gate bipolar transistor (IGBT) insulated-gate bipolar transistor (IGBT) Copper Clip Bonding Copper Clip Bonding Response Surface Response Surface
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| GB/T 7714 | Wang, Yuxiang , An, Tong , Qin, Fei . Research on optimization method of copper clip bonding package structure [J]. | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
| MLA | Wang, Yuxiang et al. "Research on optimization method of copper clip bonding package structure" . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT (2024) . |
| APA | Wang, Yuxiang , An, Tong , Qin, Fei . Research on optimization method of copper clip bonding package structure . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
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Abstract ：
The introduction of ultralow-k (ULK) materials aims to solve the back-end-of-line (BEOL) resistance and capacitance (RC) delay, but their higher porosity leads to lower fracture strength. During flip chip package integration, thermo-mechanical stresses often lead to cause chip package interaction (CPI) induced reliability problems such as interlayer dielectric (ILD) cracking or delamination. In this paper, the stress and fracture behavior of ULK in BEOL during reflow soldering of flip chip is investigated based on the sub-model approach. A 2D symmetric global model and a sub-model of Cu/ULK interconnect layer in BEOL are established using ABAQUS software. First, sub -model was inserted at different locations of the dangerous bump to identify potential high stress areas. Then, fixed length cracks were inserted in BEOL layers of the sub -model to simulate cracking. The J-integral was utilized to calculate the energy rate released (ERR) at the front edge of the 2D crack. The effect of Young's modulus of ULK on ERR was also investigated. The results show that the first principal stress peak of ULK occurs above the edge of the AL pad during reflow cooling; the ERR at the crack front edge gradually increases with the increasing number of layers; also, the ERR increases with the increasing of the modulus of ULK This study contributes to an in-depth understanding of the stress and fracture of BEOL in flip-chips during reflow soldering.
Keyword ：
Thermo-mechanical stress Thermo-mechanical stress Energy release rate Energy release rate Finite element modeling Finite element modeling Back end of line reliability Back end of line reliability Chip packaging interaction Chip packaging interaction
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| GB/T 7714 | Li, Bofu , Li, Dameng , Han, Shunfeng et al. Effect of Chip Package Interaction on Cu/Ultralow-k Interconnect Fracture in Flip Chips [J]. | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
| MLA | Li, Bofu et al. "Effect of Chip Package Interaction on Cu/Ultralow-k Interconnect Fracture in Flip Chips" . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT (2024) . |
| APA | Li, Bofu , Li, Dameng , Han, Shunfeng , Duan, Shihua , Yang, Baobin , Chen, Pei et al. Effect of Chip Package Interaction on Cu/Ultralow-k Interconnect Fracture in Flip Chips . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
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Abstract ：
For insulated gate bipolar transistor (IGBT) modules using wire bonding as the interconnection method, the main failure mechanism is cracking of the bonded interface. Studying the mechanical properties of the bonded interface is crucial for assessing the reliability of IGBT modules. In this paper, first, shear tests are conducted on the bonded interface to test the bonded interface's strength. Then, finite element-cohesive zone modeling (FE-CZM) is established to describe the mechanical behavior of the bonded interface. A novel machine learning (ML) architecture integrating a convolutional neural network (CNN) and a long short-term memory (LSTM) network is used to identify the shape and parameters of the traction separation law (TSL) of the FE-CZM model accurately and efficiently. The CNN-LSTM architecture not only has excellent feature extraction and sequence-data-processing abilities but can also effectively address the long-term dependency problem. A total of 1800 sets of datasets are obtained based on numerical computations, and the CNN-LSTM architecture is trained with load-displacement (F-delta) curves as input parameters and TSL shapes and parameters as output parameters. The results show that the error rate of the model for TSL shape prediction is only 0.186%. The performance metric's mean absolute percentage error (MAPE) is less than 3.5044% for all the predictions of the TSL parameters. Compared with separate CNN and LSTM architectures, the proposed CNN-LSTM-architecture approach exhibits obvious advantages in recognizing TSL shapes and parameters. A combination of the FE-CZM and ML methods in this paper provides a promising and effective solution for identifying the mechanical parameters of the bonded interfaces of IGBT modules.
Keyword ：
bonded interface mechanical property bonded interface mechanical property cohesive zone model cohesive zone model IGBT IGBT machine learning machine learning traction-separation relations traction-separation relations
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| GB/T 7714 | Zhao, Shengjun , An, Tong , Wang, Qi et al. Using Machine Learning and Finite Element Analysis to Extract Traction-Separation Relations at Bonding Wire Interfaces of Insulated Gate Bipolar Transistor Modules [J]. | MATERIALS , 2024 , 17 (5) . |
| MLA | Zhao, Shengjun et al. "Using Machine Learning and Finite Element Analysis to Extract Traction-Separation Relations at Bonding Wire Interfaces of Insulated Gate Bipolar Transistor Modules" . | MATERIALS 17 . 5 (2024) . |
| APA | Zhao, Shengjun , An, Tong , Wang, Qi , Qin, Fei . Using Machine Learning and Finite Element Analysis to Extract Traction-Separation Relations at Bonding Wire Interfaces of Insulated Gate Bipolar Transistor Modules . | MATERIALS , 2024 , 17 (5) . |
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Abstract ：
Femtosecond laser drilling technology has garnered significant interest in electronic packaging due to its precision and non-thermal characteristics. However, challenges like debris redeposition and energy dissipation can decrease the quality of the laser processing. This study employs femtosecond laser-induced microjet-assisted trepan drilling technique for fabricating through-holes in silicon wafers. During the processing, microjets generated by the femtosecond laser to consistently and efficiently clear ablation debris and cavitation bubbles, ensuring superior hole quality. A comparative experimental analysis with processing under identical parameters in air was conducted, demonstrating that the microjet-assisted trepan drilling technique significantly mitigates debris deposition and recast layer formation. It also enhances the roundness and straightness of the holes and boosts the material removal rate of the trepan drilling process. The fracture stability of silicon wafers processed with this technique was validated through three-point bending tests. Consequently, this study achieved the processing of highquality through -holes on silicon wafers, offering valuable insights for micro -through-hole fabrication in electronic packaging.
Keyword ：
Laser-induced microjet Laser-induced microjet Femtosecond lasertrepan drilling Femtosecond lasertrepan drilling Micro vias Micro vias
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| GB/T 7714 | Chen, Pei , Tu, Senyu , Pan, Rui et al. Experimental study on femtosecond laser-induced microj et-assisted trepan drilling of silicon wafer [J]. | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
| MLA | Chen, Pei et al. "Experimental study on femtosecond laser-induced microj et-assisted trepan drilling of silicon wafer" . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT (2024) . |
| APA | Chen, Pei , Tu, Senyu , Pan, Rui , Li, Shaowei , Qin, Fei . Experimental study on femtosecond laser-induced microj et-assisted trepan drilling of silicon wafer . | 2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2024 . |
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Abstract ：
本发明一种面向图像模型的Ansys有限元计算的自动建模方法，本发明可以实现从图像提取模型的两种及以上的不同材料区域、将像素转换成有限单元模型、定义材料属性与边界条件、定义计算分析需求与结果输出，从而高效便捷地完成有限元模型的建立以及计算过程，直接通过Ansys软件参数化设计语言文件即APDL文件进行有限元模拟计算。本发明整个过程无需其他的建模软件及有限元模拟软件的手动操作。
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| GB/T 7714 | 代岩伟 , 隗嘉慧 , 秦飞 . 一种面向图像模型的Ansys有限元计算的自动建模方法 : CN202310600830.7[P]. | 2023-05-25 . |
| MLA | 代岩伟 et al. "一种面向图像模型的Ansys有限元计算的自动建模方法" : CN202310600830.7. | 2023-05-25 . |
| APA | 代岩伟 , 隗嘉慧 , 秦飞 . 一种面向图像模型的Ansys有限元计算的自动建模方法 : CN202310600830.7. | 2023-05-25 . |
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Abstract ：
本发明公开一种焊接型IGBT模块键合线拉力测试装置及方法，拉力测试装置包括联轴器，上下两个联轴器分别用销轴安装在微拉伸机的控制器和载荷传感器上；金属拉线钩螺纹连接在上联轴器上；燕尾槽夹具，可调节IGBT模块DBC基板在横向上移动；传动装置，可调节燕尾槽夹具在纵向上移动；夹具底座，用于放置传动装置，用螺钉连接在下联轴器上；本发明可在微拉伸机上实现横向与纵向移动，并且用螺母预紧使其具有定位功能；金属拉线钩采用螺纹连接的方式可随时拆卸更换，可以用来测量不同直径的引线拉力载荷，测试过程中随着金属拉线钩的上升，微拉伸机载荷传感器可输出其载荷‑位移变化曲线，实现测量功率循环后键合线的键合强度的目的。
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| GB/T 7714 | 安彤 , 王琪 , 赵胜军 et al. 一种焊接型IGBT模块键合线拉力测试装置及方法 : CN202310403795.X[P]. | 2023-04-17 . |
| MLA | 安彤 et al. "一种焊接型IGBT模块键合线拉力测试装置及方法" : CN202310403795.X. | 2023-04-17 . |
| APA | 安彤 , 王琪 , 赵胜军 , 秦飞 . 一种焊接型IGBT模块键合线拉力测试装置及方法 : CN202310403795.X. | 2023-04-17 . |
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Abstract ：
2.5D interposer technology has gotten a lot of attention as a viable solution to high IO density, cost, and performance challenges. The thermal management of through glass vias (TGVs) is not currently being studied as much as through glass vias (TSV) heat dissipation and microfluidic design. In this paper, a creative work for the thermal performance of the memory chips based on 2.5D packaging is comprehensively studied to investigate the heat dissipation of the package. On the one hand, the idea of integrating TGV copper pillar arrays into the glass substrate is studied and refined. In order to explore the effect of TGV copper pillars for evaluating the ability of dissipating heat, a finite element model (FEM) based on CFD theory is built. According to the results, when there are more TGV copper arrays, the maximum junction temperature steadily decreases. On the other hand, the use of steady-state heat transfer methods for detecting the package's junction temperature and the execution of corresponding control tests. The experiments indicated that the maximum junction temperature of the package can be respectively decreased by 12% and 51% when silicon-based and diamond-based heat sink materials are selected.
Keyword ：
Finite Element Modeling Finite Element Modeling TGV Interposer TGV Interposer 2.5D Packaging 2.5D Packaging Thermal Management Thermal Management
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| GB/T 7714 | Zhao, Jin , Qin, Fei , Chen, Zuohuan et al. Thermal Performance of 2.5D Packaging with the Through Glass Via (TGV) Interposer [J]. | 2023 24TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2023 . |
| MLA | Zhao, Jin et al. "Thermal Performance of 2.5D Packaging with the Through Glass Via (TGV) Interposer" . | 2023 24TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT (2023) . |
| APA | Zhao, Jin , Qin, Fei , Chen, Zuohuan , Yu, Daquan . Thermal Performance of 2.5D Packaging with the Through Glass Via (TGV) Interposer . | 2023 24TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT , 2023 . |
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