A　6-bit　low-voltage　power-efficient　ash　analog-to-digital　converter　(ADC)　is　presented　in　this　paper.　The　proposed　ADC　replaces　the　conventional　voltage　comparator　with　a　new　approach　in　the　time-domain.　The　reference　voltages　and　the　analog　input　voltage　are　converted　to　digital　signal　in　a　form　of　different　pulse　widths　by　using　a　pulse-width-modulation　(PWM)　circuit.　Consequently,　the　comparison　is　achieved　by　checking　the　sequence　of　the　pulse　rising　edges　rather　than　amplifying　and　latching　the　voltage　difference.　The　total　input　capacitance　of　the　proposed　ADC　is　as　small　as　tens　of　femto-farads,　resulting　in　much　less　demand　for　the　front-end　buffer　and　the　sampling　switch.　In　addition,　an　implementation　of　the　digital　foreground　calibration　helps　to　get　rid　of　the　nonmonotonic　comparison　thresholds　due　to　mismatch.　The　calibration　operates　with　the　adaptive　comparison　threshold　by　tuning　the　modulation　level　of　the　PWM.　The　intermediate　Gray　code　conversion　increases　the　bubble　tolerance　by　1LSB.　This　digital-circuit-heavily-involved　ADC　has　been　designed　and　simulated　in　a　65　nm　CMOS　process,　achieving　35.24　dB　signal-to-noise-and-distortion-ratio　(SNDR)　at　a　sampling　rate　of　125　MS/s　while　consuming　803　mu　W　from　1V　power　supply.　As　a　result,　the　figure　of　merit　(FoM)　is　as　low　as　136　fJ/conversion-step.