An　offset　double　conversion　technique　to　calibrate　pipelined　analog-to-digital　converters　(ADCs)　is　presented,　in　which　self-equalization　is　performed　using　one　ADC,　resulting　in　fast　convergence　for　high-resolution　applications.　The　approach　also　promises　significant　improvement　of　signal-to-noise-plus-distortion　ratio　(SNDR),　simultaneous　multistage　calibration,　and　minimal　analog　circuit　modification.　The　design　tradeoffs　involved　in　this　technique,　especially　the　conversion　rate　reduction,　are　discussed　in　detail.　Behavioral　simulation　results　are　presented　to　demonstrate　the　effectiveness　of　the　technique,　in　which　the　learning　of　39　error　parameters　is　simultaneously　accomplished　with　SNDR　and　spurious-free　dynamic　range　improvements　from　43　and　52　dB　to　90　and　108　dB,　respectively,　for　a　15-bit　pipelined　ADC.