A　nonlinear　adaptive　digital　calibration　technique　for　multistage　analog-to-digital　converters　(ADCs)　is　presented.　The　approach　is　derived　from　a　replica-path　scaling　principle　inspired　by　the　parallel-ADC　equalization　architecture.　The　treatment　of　residue　gain　nonlinearities　leads　to　potentially　significant　power　savings　for　a　simple　modification　of　the　first　ADC　stage.　The　design　tradeoffs　involved　in　this　technique,　particularly　a　band-limited　interpolator　employed,　are　discussed　in　detail.　Computer　simulations　demonstrate　signal-to-noise-plus-distortion-ratio　and　spurious-free-dynamic-range　improvements　from　40　to　90　dB　and　45　to　more　than　100　dB,　respectively,　for　a　15-bit　pipelined　ADC.