Thermally　induced　residual　stresses　across　the　TSV-Cu/TiW/SiO2/Si　interface　in　through-silicon　vias　(TSVs)　have　raised　serious　concerns　about　mechanical　and　electrical　reliability　in　3D　ICs.　The　lack　of　a　nanometer-precision　measurement　technique　for　the　TSV　interfacial　stress　gradient　makes　the　interface　failure　mechanism　unclear.　In　this　work,　we　propose　an　ion　beam　layer　removal　(ILR)　method　for　determining　the　residual　stress　in　the　as-fabricated　TSV-Cu/TiW/SiO2/Si　interface　on　a　nanoscale　to　facilitate　identification　of　the　failure　mechanism　of　the　TSV-Cu/TiW/SiO2/Si　interface　in　as-fabricated　TSVs.　The　measurement　results　showed　that　the　residual　stress　fluctuates　across　the　TSV-Cu/TiW/SiO2/Si　interface　and　that　both　compressive　stress　and　tensile　stress　existed　within　the　interface　system.　Compressive　stress　occurred　at　all　three　interfaces,　the　TSV-Cu/TiW,　TiW/SiO2,　and　SiO2/Si　interfaces,　but　transitioned　to　tensile　stress　at　a　distance　of　25-45　nm　from　these　interfaces.　The　highest　level　of　shear　stress　concentration　appeared　inside　the　TSV-Cu　at　a　distance　of　approximately　45　nm　from　the　TSV-Cu/TiW　interface.　This　shear　stress　concentration　explains　the　experimentally　observed　TSV　interfacial　cracking　phenomenon.