The　conventional　analog-to-digital　converter　(ADC)　with　a　bypass　window　for　the　biomedical　applications　needs　a　fine　comparator　and　the　transistor　size　of　the　fine　comparator　is　smaller　than　the　coarse　one,　so　the　mismatch　will　be　large.　As　a　result,　this　large　mismatch　will　degrade　the　resolution　of　the　ADC,　especially,　for　the　high-resolution　applications.　A　mismatch　calibration　technique　uses　the　binary　capacitance　array　to　reduce　the　offset　voltage　of　the　comparator　is　introduced　in　this　design.　A　simulation　is　implemented　in　Cadence　to　evaluate　the　effect　of　the　calibration　technique　on　the　resolution　of　the　ADC.　The　simulation　result　shows　the　offset　voltage　of　dynamic　comparator　being　reduced　from　13.93　mV　to　3.39　mV　(one　sigma)　and　ENOB　is　improved　from　7.68　bits　to　10.0　bits　by　the　calibration　technique　in　a　180-nm　CMOS　technology.