The　image　processing　system　of　the　parallel　processor　array　will　face　the　problems　of　complex　system　structure,　long　development　period　and　the　inability　to　flexibly　adjust　and　upgrade　the　platform　hardware.　This　paper　proposes　a　design　concept　of　dynamic　reconfiguration　hardware　architecture　and　a　compatible　design.　Dynamic　reconstruction　and　dynamic　reconstructed　image　processing　system　of　image　algorithm.　At　the　same　time,　CPS1848　is　used　as　the　SRIO　switch　chip　as　the　switching　core　of　the　high-speed　data　network　and　a　switching　network　routing　method　is　designed.　Tests　have　proved　that　the　transmission　performance　of　the　system＇s　SRIO　high-speed　data　internetwork　meets　the　requirements.　Compared　with　previous　image　processing　devices,　the　system　can　flexibly　meet　the　task　requirements　of　multiple　application　scenarios;　improve　the　versatility　of　the　device　and　save　hardware　resources　and　equipment　costs.