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作者:

Fang, Juan (Fang, Juan.) (学者:方娟) | Chang, Zeqing (Chang, Zeqing.) | Cheng, Yanjin (Cheng, Yanjin.) | Zhao, Hui (Zhao, Hui.)

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CPCI-S EI Scopus

摘要:

The Heterogeneous Network-on-Chip (HNoC) integrates CPU cores, Graphic Processing Unit (GPU) cores, last-level-cache and memory controllers. The heterogeneity of this architecture inevitably brings resource contention and energy shortage. In this work, we evaluate the impact of different capacity of router buffers on communication delay and energy consumption. We run benchmarks to simulate different characteristics of the real-world applications, with the aim to balance performance with energy consumption under buffer resource limitations. Our evaluations of HNoC show that when the buffer resources are limited, by allocating more buffer to GPU, the energy consumption decrease by an average of 44.6%, while the performance degradation is negligible.

关键词:

Buffer allocation Network-on-chip GPU

作者机构:

  • [ 1 ] [Fang, Juan]Beijing Univ Technol, Fac Informat Technol, Beijing, Peoples R China
  • [ 2 ] [Chang, Zeqing]Beijing Univ Technol, Fac Informat Technol, Beijing, Peoples R China
  • [ 3 ] [Cheng, Yanjin]Beijing Univ Technol, Fac Informat Technol, Beijing, Peoples R China
  • [ 4 ] [Zhao, Hui]Univ North Texas, Comp Sci & Engn Dept, Denton, TX 76203 USA

通讯作者信息:

  • 方娟

    [Fang, Juan]Beijing Univ Technol, Fac Informat Technol, Beijing, Peoples R China

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来源 :

2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)

ISSN: 2159-3469

年份: 2018

页码: 744-749

语种: 英文

被引次数:

WoS核心集被引频次: 3

SCOPUS被引频次: 3

ESI高被引论文在榜: 0 展开所有

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