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作者:

Cai, Min (Cai, Min.) | Gu, Zhi-min (Gu, Zhi-min.) | Ji, Jun-zhong (Ji, Jun-zhong.) (学者:冀俊忠) | Fang, Juan (Fang, Juan.) (学者:方娟) | Li, Bin (Li, Bin.)

收录:

CPCI-S

摘要:

This paper proposes the helper thread prefetch request breakdown to differentiate between different performance gains achieved by different helper thread prefetch parameter combinations. Cycle-accurate simulation results of selected benchmarks in Olden and CPU2006 show that, the selection of appropriate helper thread prefetching parameters can maximize the potential of helper thread prefetching, based on the different memory access patterns of target applications.

关键词:

Helper thread Prefetch breakdown Shared cache chip multiprocessors

作者机构:

  • [ 1 ] [Cai, Min]Beijing Univ Technol, Coll Comp Sci, Beijing 100124, Peoples R China
  • [ 2 ] [Ji, Jun-zhong]Beijing Univ Technol, Coll Comp Sci, Beijing 100124, Peoples R China
  • [ 3 ] [Fang, Juan]Beijing Univ Technol, Coll Comp Sci, Beijing 100124, Peoples R China
  • [ 4 ] [Gu, Zhi-min]Beijing Inst Technol, Sch Comp Sci & Technol, Beijing 100081, Peoples R China
  • [ 5 ] [Li, Bin]Chinese Acad Sci, Inst Software, Beijing 100190, Peoples R China

通讯作者信息:

  • [Cai, Min]Beijing Univ Technol, Coll Comp Sci, Beijing 100124, Peoples R China

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来源 :

COMPUTER SCIENCE AND TECHNOLOGY (CST2016)

年份: 2017

页码: 64-72

语种: 英文

被引次数:

WoS核心集被引频次: 0

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