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Abstract:
3D IC is developing rapidly, but there is no mature physical design. A 3D chip physical design method contains hierarchical process, memory and TSV localization process, as well as hierarchical physical design process is proposed in this paper. By splitting the netlist, memory and logic are layered up and down. And the upper memories and TSV cells are placed automatically by implemented the localization algorithm. Each layer can be routed separately. It is concluded that this physical design method is feasible and the processes can be compatible in 2D EDA tools.
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Source :
PROCEEDINGS OF 2017 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS (ICEMI), VOL 1
Year: 2017
Page: 151-154
Language: English
Cited Count:
WoS CC Cited Count: 0
SCOPUS Cited Count:
ESI Highly Cited Papers on the List: 0 Unfold All
WanFang Cited Count:
Chinese Cited Count:
30 Days PV: 1
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