A memory-logic separated 3D chip physical design - 文章详情页

作者：

Zhang Shier (Zhang Shier.) | Hou Ligang (Hou Ligang.) | Ye Tongyang (Ye Tongyang.) | Wang Jinhui (Wang Jinhui.) | Peng Xiaohong (Peng Xiaohong.)

收录：

CPCI-S

摘要：

3D　IC　is　developing　rapidly,　but　there　is　no　mature　physical　design.　A　3D　chip　physical　design　method　contains　hierarchical　process,　memory　and　TSV　localization　process,　as　well　as　hierarchical　physical　design　process　is　proposed　in　this　paper.　By　splitting　the　netlist,　memory　and　logic　are　layered　up　and　down.　And　the　upper　memories　and　TSV　cells　are　placed　automatically　by　implemented　the　localization　algorithm.　Each　layer　can　be　routed　separately.　It　is　concluded　that　this　physical　design　method　is　feasible　and　the　processes　can　be　compatible　in　2D　EDA　tools.

关键词：

3D IC TSV Physical Design EDA

作者机构：

[ 1 ] [Zhang Shier]Beijing Univ Technol, VLSI, Beijing 100124, Peoples R China
[ 2 ] [Hou Ligang]Beijing Univ Technol, VLSI, Beijing 100124, Peoples R China
[ 3 ] [Ye Tongyang]Beijing Univ Technol, VLSI, Beijing 100124, Peoples R China
[ 4 ] [Peng Xiaohong]Beijing Univ Technol, VLSI, Beijing 100124, Peoples R China
[ 5 ] [Zhang Shier]Beijing Univ Technol, Syst Lab, Beijing 100124, Peoples R China
[ 6 ] [Hou Ligang]Beijing Univ Technol, Syst Lab, Beijing 100124, Peoples R China
[ 7 ] [Ye Tongyang]Beijing Univ Technol, Syst Lab, Beijing 100124, Peoples R China
[ 8 ] [Peng Xiaohong]Beijing Univ Technol, Syst Lab, Beijing 100124, Peoples R China
[ 9 ] [Wang Jinhui]North Dakota State Univ, Dept Elect & Comp Engn, Fargo, ND 58102 USA

通讯作者信息：

[Hou Ligang]Beijing Univ Technol, VLSI, Beijing 100124, Peoples R China;;[Hou Ligang]Beijing Univ Technol, Syst Lab, Beijing 100124, Peoples R China

电子邮件地址：

houligang@bjut.edu.cn

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