Based　on　the　Synopsys　physical　design　tool　IC　Compiler,　taking　the　design　of　BES6799　chip　under　SMIC　0.18　mu　m　Logic　1P5M　process　as　an　example,　this　paper　analyzed　and　compared　the　clock　skew　and　clock　cell　area　of　clock　trees　which　are　built　by　three　methods,　such　as　inserting　inverter,　buffer,　combination　of　both.　It　was　found　that　the　clock　tree　completed　with　buffers　has　a　better　clock　skew　and　the　clock　cell　areas　are　almost　the　same.　So　buffer　is　selected　as　the　clock　delay　cell　to　build　clock　tree.　In　order　to　further　reduce　the　clock　skew　and　then　make　timing　closure,　the　clock　tree　synthesis　method　which　the　important　clocks　are　synthesized　first　is　proposed.　It　was　shown　that　the　method　can　effectively　reduce　the　clock　skew　and　clock　cell　area.　Based　on　the　above　methods,　the　chip　was　finally　taped　out　in　SMIC.