In　recent　years,　high　performance　computing　systems　have　obtained　more　processing　cores　and　shared　a　last　level　cache　(LLC).　Now,　the　problem　to　the　existing　cache　partitioning　techniques　is　that　they　give　each　core　the　number　of　cache　ways　according　to　their　need,　these　schemes　have　the　potential　to　realize　significant　performance　increases,　yet　for　most　part　they　do　not　consider　LLC　energy　saving.　In　this　paper,　we　design　and　realize　a　multi-processing　processor　monitor.　Through　a　utility　monitor　we　calculate　the　number　of　hits　and　misses　when　allocate　different　cache　ways　to　each　application.　In　other　words,　we　use　utility　monitors　to　track　the　access　by　each　core　to　characterize　each　thread＇s　use　of　the　cache.　Dynamically　give　each　core　the　number　of　ways　based　on　the　performance　to　achieve　its　highest　utilization.　On　gem5,　we　run　Parsec　benchmarks　as　our　multi-threaded　application.　We　output　the　numbers　of　misses　for　all　possible　number　of　ways,　and　find　the　number　of　associativity　to　achieve　its　highest　utilization.　By　analysing　experimental　results,　cache　miss　rate　decreases　with　the　increasing　of　the　cache　capacity.