Design of high-accuracy decimal frequency divider with Verilog-HDL - 文章详情页

作者：

Ma, Shaowei (Ma, Shaowei.) | Guan, Baolu (Guan, Baolu.) | Hou, Ligang (Hou, Ligang.)

收录：

CPCI-S

摘要：

This　paper　presents　a　more　complex　algorithm　with　Verilog-HDL,　which　based　on　the　dual-modulus　preseted　decimal　frequency　divider.　This　algorithm　can　not　only　increase　the　accuracy　of　decimal　frequency　divider.,　but　also　can　be　used　to　divide　a　clock.　Simulations　are　conducted　to　analyze　the　characteristics　of　the　decimal　frequency　divider　and　DDS　divider.　The　results　shows　that　the　divider　can　satisfy　the　requirements　of　design.

关键词：

DDS Decimal frequency divider Verilog-HDL

作者机构：

[ 1 ] [Ma, Shaowei]Beijing Univ Technol, VLSI & Syst Lab, Beijing 10024, Peoples R China
[ 2 ] [Guan, Baolu]Beijing Univ Technol, VLSI & Syst Lab, Beijing 10024, Peoples R China
[ 3 ] [Hou, Ligang]Beijing Univ Technol, VLSI & Syst Lab, Beijing 10024, Peoples R China

通讯作者信息：

[Ma, Shaowei]Beijing Univ Technol, VLSI & Syst Lab, Beijing 10024, Peoples R China

电子邮件地址：

mashaowei@emails.bjut.edu.cn

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