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作者:

Fang, Juan (Fang, Juan.) (学者:方娟) | She, Chaojie (She, Chaojie.) | Yu, Lu (Yu, Lu.)

收录:

CPCI-S

摘要:

With the craft and application technology continue to evolve, progress, on-chip multi-core technology becomes more mature, however, with the size of the on-chip processor becomes larger and larger, the number of integrated processor cores becomes more and more large, which leads to the technology of NoC(Network On Chip) consisted by the processor cores and other components having greater influence on overall performance of multi-processor system. Different network topologies and routing scheduling will affect the overall performance, such as execution time, network latency, power consumption, etc. So in this paper, we referred a new topology between cores and other components, adding more interconnections and setting different weight for every links. Then adjusted communication scheduling of router, changing port sequence being checked dynamically, which improved the situation of communication, reduced the latency of network and running time, increased the throughput of network and improved the instruction per cycle. Through the improvement the network latency reduced 9%-10% compared with present scheme, and as the number of cores increasing the procedure execution time reduced 8%-9%, instruction per cycle increased 3%-5%. Effect will be more pronounced with the cores and tasks increasing.

关键词:

作者机构:

  • [ 1 ] [Fang, Juan]Beijing Univ Technol, Coll Comp Sci, Beijing 100124, Peoples R China
  • [ 2 ] [She, Chaojie]Beijing Univ Technol, Coll Comp Sci, Beijing 100124, Peoples R China
  • [ 3 ] [Yu, Lu]Beijing Univ Technol, Coll Comp Sci, Beijing 100124, Peoples R China

通讯作者信息:

  • 方娟

    [Fang, Juan]Beijing Univ Technol, Coll Comp Sci, Pingleyuan 100, Beijing 100124, Peoples R China

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来源 :

PROCEEDINGS OF THE 2013 ASIA-PACIFIC COMPUTATIONAL INTELLIGENCE AND INFORMATION TECHNOLOGY CONFERENCE

年份: 2013

页码: 8-15

语种: 英文

被引次数:

WoS核心集被引频次: 10

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ESI高被引论文在榜: 0 展开所有

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