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Author:

Liu, Fei (Liu, Fei.) | Li, Haitao (Li, Haitao.)

Indexed by:

CPCI-S

Abstract:

Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. In this paper, we give the different initial step for different modulation and present a hardware implementation of the extended min-sum (EMS) decoding algorithm for non-binary LDPC codes. Moreover, an FPGA simulation over GF(16) is given to demonstrate the efficiency of the presented techniques.

Keyword:

EMS NB-LDPC Architecture

Author Community:

  • [ 1 ] [Liu, Fei]Beijing Univ Technol, Coll Elect Informat & Control Engn, Beijing 100124, Peoples R China
  • [ 2 ] [Li, Haitao]Beijing Univ Technol, Coll Elect Informat & Control Engn, Beijing 100124, Peoples R China

Reprint Author's Address:

  • [Liu, Fei]Beijing Univ Technol, Coll Elect Informat & Control Engn, Beijing 100124, Peoples R China

Email:

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Source :

2011 7TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING (WICOM)

Year: 2011

Language: English

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 2

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