Non-binary　low-density　parity-check　(NB-LDPC)　codes　can　achieve　better　error-correcting　performance　than　binary　LDPC　codes　when　the　code　length　is　moderate.　In　this　paper,　we　give　the　different　initial　step　for　different　modulation　and　present　a　hardware　implementation　of　the　extended　min-sum　(EMS)　decoding　algorithm　for　non-binary　LDPC　codes.　Moreover,　an　FPGA　simulation　over　GF(16)　is　given　to　demonstrate　the　efficiency　of　the　presented　techniques.