A DC-Offset Cancellation Circuit for PGA in Baseband Communication - 文章详情页

作者：

Huang, Guanzhong (Huang, Guanzhong.) | Wu, Yingjie (Wu, Yingjie.) | Zhong, Chaoli (Zhong, Chaoli.) | Lin, Pingfen (Lin, Pingfen.)

收录：

CPCI-S

摘要：

This　paper　introduces　a　novel　DC-offset　cancellation　circuit　for　PGA　in　baseband　communication.　The　output　DC-offset　is　reduced　from　over　one　hundred　millivolts　to　less　than　4mV　in　all　cases　with　power　dissipation　of　6.6　mu　W.　At　the　same　time,　spurious-free　dynamic　range　(SFDR)　of　PGA　output　is　51.4dB　and　the　settling　time　of　63dB　gain　step　switching　is　372　mu　s.　The　chip　is　fabricated　in　0.18　mu　m　CMOS　technology.

关键词：

作者机构：

[ 1 ] [Huang, Guanzhong]Beijing Univ Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China
[ 2 ] [Wu, Yingjie]Beijing Univ Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China
[ 3 ] [Zhong, Chaoli]Beijing Univ Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China
[ 4 ] [Lin, Pingfen]Beijing Univ Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China

通讯作者信息：

[Huang, Guanzhong]Beijing Univ Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China

电子邮件地址：

huanggz@emails.bjut.edu.cn

查看成果更多字段

成果类型
所属机构

所有年份指定年份从至