This　paper　describes　the　architecture　of　Reed-Solomon　Decoder　used　to　decode　RS　code　with　variable　block　length　n　as　well　as　message　length　k.　Furthermore,　the　error-correcting　capability　t　can　be　changed　at　every　RS　code　block.　The　decoder　permits　3-step　processing:　syndromes　calculation,　modified　Euclidean　algorithm　and　error　information　calculation.　And　the　most　important　step　is　the　modified　Euclidean　algorithm　for　computing　the　error-locator　polynomial　and　error-evaluator　polynomial.　The　decoder　has　been　designed　in　Verilog　HDL,　and　successfully　synthesis　in　a　FPGA　chip.