A　simple　DFT(Design　For　Test)　Evaluation　Methodology　is　introduced　in　this　paper　DFT　technique　is　necessary　in　today＇s　ASIC　design.　It　offers　the　only　way　to　detect　fault　in　ASICs　with　millions　or　billions　of　gates　after　manufactured.　Problems　arose　when　ASICs　with　a　number　of　build-in　memory　blocks　is　designed.　The　work　done　by　DFT　in　this　situation　tighten　the　timing　budget　and　make　the　whole　design　fail　to　meet　the　specification.　In　our　video　decoder　chip　design,　we　encountered　this　problem.　We　adopted　three　plan　according　to　different　DFT　plan:　the　first　one,　scan　chain　insertion,　control　logic　concerning　memory,　test　points　and　memory　BIST　are　applied.　The　second　one,　scan　chain　insertion　and　memory　BIST　are　applied.　The　third　one,　only　memory　BIST　is　applied.　The　whole　chip　design　flow　need　time　and　effort.　Therefore　a　simple　DFT　evaluation　methodology　called　Timing　Decision　(TD)　is　introduced.　Different　DFT　plans　are　evaluated　by　TD　with　the　successful　realization　of　the　chip＇s　design　specification.　According　to　the　TD　＇s　requirement,　the　three　DFT　plans　were　implemented　partly　through　the　whole　design　flow　and　compared　on　functionality,　chip　area,　timing　and　design　complexity.　Results　show　that　DFT　should　be　partly　adopted　in　specific　situation　like　multi　built-in　memory　ASIC　design,　and　TD　can　save　engineer＇s　effort　with　a　precise　estimation　on　DFT　plan　adoption.