A　digital　phase-locked　loop　(DPLL)　based　on　a　new　digital　phase-frequency　detector　(DPFD)　is　presented.　The　self-calibration　technique　is　employed　to　acquire　fast　acquisition,　low-jitter　and　wide　frequency　range.　The　DPLL　works　from　60　to　600　MHz　with　a　maximum　power　consumption　of　3.5mW　at　a　supply　voltage　of　1.8V.　It　also　features　a　fractional-N　synthesizer　with　digital　2(nd)-order　sigma-delta　noise　shaping,　which　can　achieve　the　small　step　size　and　improved　phase-noise　spectrum.　The　DPLL　has　been　implemented　in　a　0.18　mu　m　quintuple-metal　CMOS　process.　The　peak-to-peak　jitter　is　less　than　0.25%　of　the　output　period　(T-out).　and　the　lock　time　is　less　than　150　times　of　the　reference　clock　period　after　the　pre-divider　(T-pre).