This　paper　presents　a　digital　adaptive　calibration　method　to　overcome　the　effect　of　timing　mismatches　in　the　time-interleaved　analog-to-digital　converter　(TIADC).　The　structure　of　the　channel　splitting-recombining　is　proposed.　The　TIADC　with　M　channels　is　divided　into　log(2)M　stages　for　calibration,　and　each　stage　is　composed　of　one　or　more　two-channel　sub-systems.　The　Lagrange　mean　value　difference　of　adjacent　channels　is　constructed　by　arithmetical　approximation　to　estimate　the　timing　mismatch.　It　does　not　need　to　oversample　the　bandlimited　input　signal　with　an　oversampling　ratio.　And　it　does　not　require　the　input　signal　to　have　significant　power　over　its　bandwidth　for　identification.　Timing　mismatches　are　corrected　by　the　cascaded　differentiator-multipliers.　A　reuse　structure　is　developed　to　reduce　the　consumption　of　hardware　resources.　Simulation　results　of　the　four-channel　TIADC　show　that　the　spurious-free　dynamic　range　(SFDR)　can　be　improved　from　31.19　to　73.39　dB.　Hardware　implementation　based　on　FPGA　is　also　carried　out,　and　the　corrected　SFDR　is　measured　at　72.29　dB.　The　approach　has　low　complexity,　and　the　bandwidth　of　the　input　signal　can　reach　the　Nyquist　bandwidth　of　the　complete　TIADC　system.