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作者:

Yang, Jiang (Yang, Jiang.) | Xiao, Yile (Xiao, Yile.) | Li, Dejian (Li, Dejian.) | Li, Zheng (Li, Zheng.) | Chen, Zhijie (Chen, Zhijie.) | Wan, Peiyuan (Wan, Peiyuan.)

收录:

CPCI-S

摘要:

A configurable SPI interface based on APB bus is proposed in this paper. The SPE interface transmission information is configured through APB bus, which can realize the master-slave mode switching, 4 kinds of clock transmission mode switching and MSB/LSB communication mode switching. Meanwhile the transmission rate can be selected and the transmission length can he variable from 1 to 32 hits. Based on the SPI transmission protocol, the proposed design uses a finite state machine method to control the transmission timing of the SPI interface. The design was verified through RTL simulation and FPGA verification. The verification results show that the functional of SPI interface is correct and the data transmission is stable.

关键词:

APB bus Configurable FPGA SPI interface

作者机构:

  • [ 1 ] [Yang, Jiang]Beijing Univ Technol, Fac Informat Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China
  • [ 2 ] [Chen, Zhijie]Beijing Univ Technol, Fac Informat Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China
  • [ 3 ] [Wan, Peiyuan]Beijing Univ Technol, Fac Informat Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China
  • [ 4 ] [Xiao, Yile]Beijing Smartchip Microelect Technol Co Ltd, Beijing, Peoples R China
  • [ 5 ] [Li, Dejian]Beijing Smartchip Microelect Technol Co Ltd, Beijing, Peoples R China
  • [ 6 ] [Li, Zheng]Beijing Smartchip Microelect Technol Co Ltd, Beijing, Peoples R China

通讯作者信息:

  • [Wan, Peiyuan]Beijing Univ Technol, Fac Informat Technol, Beijing Embedded Syst Key Lab, Beijing, Peoples R China

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来源 :

2020 IEEE 14TH INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY, AND IDENTIFICATION (ASID)

ISSN: 2163-5048

年份: 2020

页码: 73-76

语种: 英文

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