This　paper　presents　a　9-bit　1　GS/s　successive　approximation　register　(SAR)　analog-to-digital　converter　(ADC).　In　this　hybrid　architecture,　the　pseudo-pipeline　operation　is　realized,　which　increases　the　sampling　rate　effectively.　The　ADC　adopts　two　key　technologies:　the　variable　gain　voltage-to-time　converter　(VTC),　which　ensures　the　linearity　is　not　sacrificed;　the　segmented　time-to-digital　converter　(STDC),　which　further　improves　the　linearity　of　time　domain　quantization.　The　prototype　ADC　is　simulated　in　a　standard　65-nm　CMOS　process　with　an　active　area　of　0.038　mm(2).　The　simulated　SNDR　and　SFDR　are　44.3　and　58　dB　with　a　sampling　rate　of　1　GS/s.　The　FoMW　and　FoMS　are　24.7　fJ/conv-step　and　150.7　dB,　respectively.