This　paper　studies　the　effects　of　process　node　and　circuit　schemes　on　the　electromagnetic　susceptibility　(EMS)　of　current　reference　circuits.　Three　reference　circuits　using　PDSOI　with　technology　node　of　0.5　μm　(VREF50),　0.35　μm　(VREF33)　and　0.18　μm　(VREF18)　are　used.　VREF50　has　an　additional　CASCODE　structure　to　achieve　a　PSRR　enhancement.　The　test　results　show　that　when　the　electromagnetic　interference　(EMI)is　injected　into　the　terminals　VDD　and　VSS,　the　reference　currents　in　both　of　the　three　circuits　exhibit　a　negative　shift.　The　main　reason　is　that　the　drain　voltage　of　the　transistor　close　to　the　terminal　VDD　fluctuates　greatly,　causing　a　deviation　from　the　saturation　to　the　linear　region　from　time　to　time,　hence　reducing　the　average　value　of　the　current.　The　higher　voltage　margin　with　the　large　process　node,　the　stronger　the　immunity　of　the　reference　circuit　to　EMI.　It　is　worth　noting　that　the　CASCODE　structure　has　a　negative　effect　on　low　frequency　large-signal　EMI.　Therefore,　VREF50　and　VREF33　have　the　similar　EMS.　In　a　higher　frequency　range,　the　parasitic　effect　brought　by　the　CASCODE　structure　becomes　more　serious,　which　increases　the　high-frequency　impedance　of　the　circuit.　Finally,　simulation　results　imply　that　the　immunity　level　is　improved　by　decreasing　bypass　capacitor　between　the　sensitive　node　and　the　VDD　to　reduce　the　EMI　injection,　and　replacing　the　nonlinear　device　by　a　positive　temperature　coefficient　resistor　to　improve　the　circuit　linearity.　©　2020　Elsevier　Ltd