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作者:

Zhang, Min (Zhang, Min.) | Dai, Yanwei (Dai, Yanwei.) | Qin, Fei (Qin, Fei.) | Jin, Yifan (Jin, Yifan.)

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EI Scopus

摘要:

Through Silicon Via copper (TSV-Cu) is the crucial element for chips stacking and 3D packaging vertically. During the TSV-Cu manufacturing, annealing process is essential to relive the residual stress inner the TSV-Cu and stabilize the microstructure of Cu grain. However, the annealing process usually leads to TSV-Cu protrusions, which have to be flattened by chemical mechanical polishing (CMP) to perform subsequent process. Subsequent process concerned with high temperature treatments will continue to result in a second protrusion of TSV-Cu, which threatens the reliability of interconnect structures above the TSV. In this paper, the effects of various annealing heating rates on protrusions of TSV-Cu and its microstructure evolution are investigated. The influences of grain size and grain boundary types for TSV-Cu under various heating rates on protrusions are analyzed and discussed. © 2022 IEEE.

关键词:

Grain boundaries Microstructure Electronics packaging Integrated circuit interconnects Silicon Three dimensional integrated circuits Heating rate Annealing Chemical mechanical polishing Copper

作者机构:

  • [ 1 ] [Zhang, Min]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability, Faculty of Materials and Manufacturing, Beijing, China
  • [ 2 ] [Dai, Yanwei]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability, Faculty of Materials and Manufacturing, Beijing, China
  • [ 3 ] [Qin, Fei]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability, Faculty of Materials and Manufacturing, Beijing, China
  • [ 4 ] [Jin, Yifan]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability, Faculty of Materials and Manufacturing, Beijing, China

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年份: 2022

语种: 英文

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