This　paper　introduces　four　different　designs　of　the　comparator　in　recent　years.　The　edge-pursuit　comparator　(EPC),　which　is　a　new　energy-efficient　ring　oscillator　collapse-based　comparator,　can　automatically　scale　comparison　energy　according　to　its　input　difference　and　eliminating　unnecessary　energy.　To　reduce　the　energy　consumption,　the　pre-amplifier　output　node　of　a　dynamic　bias　comparator　(DBC)　partially　discharge　by　adding　a　tail　capacitor.　The　novel　two-stage　dynamic　comparator　with　a　transconductance-enhanced　latching　stage　efficiently　decreases　the　delay　and　energy　consumption.　Furthermore,　an　improvement　of　the　traditional　comparator　for　precise　application　is　introduced.　The　new　comparator　applies　PMOS　transistors　at　the　input　of　the　preamplifier　and　the　latch　stage,　and　both　are　controlled　by　a　special　clock　generator　which　lets　the　new　comparator　achieve　optimum　delay　and　with　no　excess　power　consumption.　This　paper　describes　each　comparator　in　detail　and　compares　different　features　of　them.　©　2022　SPIE.