This　paper　reports　a　wafer　level　3D　integrated　passive　devices　(3D　IPD)　package　design,　fabrication　processes,　and　reliability　aspects.　The　key　process　including　through　glass　vias　(TGV)　vertical　interconnection,　fine　pitch　RDLs　formation,　dielectric　layer　deposition,　passivation　layer　and　ball-grid　array　formation,　are　developed.　In　addition,　a　finite　element　model　was　built　to　analyze　the　TGV　stress　distribution　and　wafer　warpage　evolution　during　the　annealing　process.　The　maximum　principal　stress　can　be　decreased　by　reducing　the　thermal　mismatch　strain　between　glass　and　copper,　and　hence　lowering　the　risk　of　TGV　cracking.　The　results　show　that　when　the　CTE　increases　from　3.2　ppm/°C　to　7.58　ppm/°C　for　glass　substrate,　the　maximum　principal　stress　at　the　edge　of　the　TGV　is　reduced　by　20%.　This　work　is　expected　to　serve　as　IPD　with　TGV　reference　platform　which　can　provide　improvement　measures　for　3D　vertical　interconnection　applications.　©　2022　IEEE.