Through　silicon　via　(TSV)　and　stacked　bonding　are　the　core　technologies　to　perform　vertical　interconnect　for　3D　integration.　For　wafer-level　multilayer　stacking　process,　thermal　stress　is　generated　and　accumulated　due　to　the　difference　in　thermal　expansion　coefficients　of　materials　in　each　layer　of　the　structure.　Due　to　the　large　thermal　stress,　the　issue　of　failures　in　the　stacking　process　are　caused　by　solder　joints　almost.　Hence,　thermal　stress　analyses　for　multilayer　stacking　process　are　in　urgent　need.　In　this　paper,　a　finite　element　model　(FEM)　is　established　to　investigate　the　reliabilities　for　six　layered　TSV　wafer　bonded.　Selected　the　General　Plane　Deformation　(GPD)　FEM　model　as　the　simulation　model　for　conserving　computer　resources　and　time　because　of　the　large　number　of　TSVs.　Birth　and　death　element　technology　is　applied,　and　descripted　the　procedure　during　the　six　layered　wafer　staking　process.　Considered　three　kinds　of　solder　joint　materials　for　SAC305,　Sn63Pb37　and　Sn10Pb90,　and　analyzed　the　von　Mises　stress　and　equivalent　plastic　strain.　©　2022　IEEE.