In　this　paper,　we　analyse　the　existing　C　code　for　the　Bayesian　deconvolution　algorithm,　and　propose　an　improved　scheme　for　a　CPU　platform.　The　improved　algorithm　is　implemented　on　an　FPGA　and　functional　verification　is　performed.　A　complete　FPGA　hardware　acceleration　system　is　then　constructed　to　realize　data　communication　and　computation　between　the　FPGA　and　the　upper-level　computer.　Four-way　parallel　computation　on　the　FPGA　platform　is　designed　and　optimized　to　improve　the　computational　efficiency.　The　algorithm　is　implemented　through　dedicated　hardware　servers　to　protect　the　intellectual　property　of　the　software　algorithm.　©　2023　SPIE.