This　paper　proposed　a　low-power-oriented　cache　design　(LPD)　for　L2　cache　of　multi-core　processors.　We　developed　two　methods　to　lower　cache　power　consumption:　LPHP　(low　power-oriented　hybrid　cache　partition　algorithm)　and　WPP-L2　(way-prediction　based　on　a　cache　partition　algorithm).　The　LPD　considers　these　two　different　ways　to　reduce　power　consumption　meanwhile　to　produce　the　best　possible　cache　performance.　In　LPHP,　we　closed　the　columns　that　are　not　in　use.　In　WPP-L2,　we　predicted　an　appropriate　way　before　cache　access　that　can　reduce　the　access　time　to　save　power.　Experiments　show　that　LPHP　can　reduce　power　consumption　by　23.7%　and　WPP-L2　can　reduce　17.2%　on　average.　In　comparison　with　the　traditional　LRU　strategy,　these　algorithms　have　little　effect　on　the　cache　performance　and　sometimes　improve　the　throughput.　©　2015,　by　Binary　Information　Press