An　unity-gain　1-bit　flip-around　digital-to-analog　converter　(FADAC),　without　any　capacitor　matching　issue,　is　proposed　as　the　front-end　input　stage　in　a　pipelined　analog-to-digital　converter　(ADC),　allowing　an　input　signal　voltage　swing　up　to　be　doubled.　This　large　input　swing,　coupled　with　the　inherent　large　feedback　factor　(ideally　beta　=　1)　of　the　proposed　FADAC,　enables　a　power-efficient　low-voltage　high-resolution　pipelined　ADC　design.　The　1-bit　FADAC　is　exploited　in　a　SHA-less　and　opamp-sharing　pipelined　ADC,　exhibiting　12-bit　resolution　with　an　input　swing　of　1.8　Vpp　under　a　1.1　V　power　supply.　Fabricated　in　a　0.13-mu　m　CMOS　process,　the　prototype　ADC　achieves　a　measured　signal-to-noise　plus　distortion　ratio　(SNDR)　of　66.4　dB　and　a　spurious-free　dynamic　range　(SFDR)　of　76.7　dB　at　20　MS/s　sampling　rate.　The　ADC　dissipates　5.2　mW　of　power　and　occupies　an　active　area　of　0.44　mm(2).　The　measured　differential　nonlinearity　(DNL)　is　+0.72/-0.52　least　significant　bit　(LSB)　and　integral　nonlinearity　(INL)　is　+0.84/-0.75　LSB　at　a　3-MHz　sinusoidal　input.