To　reduce　the　power　consumption　and　heat　density　of　processors,　an　energy-saving　scheme　suitable　for　the　multi-core　and　multi-threaded　architecture　was　proposed,　which　dynamically　activates,　closes　or　restricts　the　on-chip　resources　according　to　the　actual　run-time　needs　so　as　to　reduce　power　consumption　while　the　performance　is　maintained.　In　order　to　accurately　validate　the　dynamic　reconfiguration　scheme　proposed,　Simics　was　used　to　simulate　a　whole　system　SPARC　platform　and　SPEC　OMP　benchmark　was　adopted　for　validation.　The　results　showed　the　proposed　solution　reduces　power　consumption　by　18.13%　and　improves　performance　by　40.1%　compared　to　the　traditional　static　partitioning　scheme.　©,　2014,　Northeastern　University.　All　right　reserved.