Comparative evaluation of an error checking approach for MPSoC - 文章详情页

作者：

Liu, Tang (Liu, Tang.) | Qin, Huang-Zhang (Qin, Huang-Zhang.) | Bin, Hou-Yi (Bin, Hou-Yi.) | Cai, Fang-Feng (Cai, Fang-Feng.) | Bing, Zhang-Hui (Bing, Zhang-Hui.)

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摘要：

This　paper　proposes　a　hardware　error　checking　approach　(CCRC)　by　using　redundancy　core　for　multiprocessor　system-on-chip　(MPSoC)　and　describes　several　main　error　detection　methods　based　on　Software-Implemented　Hardware　Fault　Tolerance　(SHIF)　idea　proposed　in　literatures.　The　CCRC　approach　insert　some　error　detection　code　in　high　level　code,　detect　the　existing　of　redundancy　core　in　MPSoC,　then　complete　the　calculation　of　detection　code　in　redundancy　core.　The　author　compares　the　CCRC　approach　with　several　main　error　detection　methods　on　error　detection　capabilities,　area,　memory　and　performance　overheads　in　an　experiment　platform.　The　result　of　comparative　evaluation　shows　that　the　CCRC　approach　is　effective　for　MPSoC,　taking　some　advantages　in　versatility　and　lower　cost.　©　2013　SERSC.

关键词：

Multiprocessing systems Microprocessor chips Redundancy Hardware Error detection

作者机构：

[ 1 ] [Liu, Tang]Embedded Software and Systems Institutes, Beijing University of Technology, China
[ 2 ] [Liu, Tang]Department of Physics and Electronics Engineering, Guangxi Teachers Education University, Nanning, 530024, China
[ 3 ] [Qin, Huang-Zhang]Embedded Software and Systems Institutes, Beijing University of Technology, China
[ 4 ] [Bin, Hou-Yi]Embedded Software and Systems Institutes, Beijing University of Technology, China
[ 5 ] [Cai, Fang-Feng]Department of Physics and Electronics Engineering, Guangxi Teachers Education University, Nanning, 530024, China
[ 6 ] [Bing, Zhang-Hui]Department of computer science and Electronics Engineering, GuiLin University of Electronic Technology, GuiLin, 541004, China

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