High-resolution power-efficient delta-sigma digital-to-analog converter - 文章详情页

作者：

Liu, Su-Juan (Liu, Su-Juan.) | Yang, Yue (Yang, Yue.) | Ding, Nan-Jing (Ding, Nan-Jing.) | Chen, Jian-Xin (Chen, Jian-Xin.)

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EI Scopus PKU CSCD

摘要：

In　this　paper,　a　96　dB　stereo　audio　Delta-Sigma　Digital-to-Analog　Converter　(DAC)　is　designed.　The　4th-order　one　bit　cascade　of　integrators　with　distributed　feedback　(CIFB)　is　applied　for　its　distinct　linearity　to　acquire　high　resolution.　For　decreasing　the　chip　area　and　power　consumption,　the　delta-sigma　modulator　and　the　interpolator　filter　are　multiplexed　by　the　two　channels.　With　the　coefficients　of　filter　CSD　coded,　the　interpolator　filter　is　multiplier-free.　The　feedback　and　forward　back　factors　of　the　modulator　are　optimized　to　accomplish　a　multiplier-free　stable　system.　The　design　is　fabricated　on　TSMC　0.18　μm　1.8　V/3.3　V　1P5M　CMOS　process.　The　chip　occupies　1.12　mm2　and　dissipates　only　18.7　mW　power.　The　measurement　results　show　that,　the　DAC　achieves　96.7　dB　SNR　over　the　24　kHz　audio　band　and　meets　the　design　specification.

关键词：

Delta sigma modulation Digital to analog conversion Feedback Interpolation Modulators Signal to noise ratio

作者机构：

[ 1 ] [Liu, Su-Juan]College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing 100124, China
[ 2 ] [Yang, Yue]College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing 100124, China
[ 3 ] [Ding, Nan-Jing]College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing 100124, China
[ 4 ] [Chen, Jian-Xin]College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing 100124, China

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