Charge self-compensation technology research for low power and high performance domino circuits - 文章详情页

作者：

Wang, Jinhui (Wang, Jinhui.) | Gong, Na (Gong, Na.) | Hou, Ligang (Hou, Ligang.) | Wu, Wuchen (Wu, Wuchen.) (学者：吴武臣) | Dong, Limin (Dong, Limin.)

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摘要：

A　charge　self-compensation　technology　is　proposed　in　this　paper　to　lower　the　active　power　and　improve　the　performance　of　domino　circuits.　Domino　circuits　with　different　structures　of　pull-up　network　(PUN)　and　pull-down　network　(PND)　are　designed　u-sing　charge　self-compensation　technology　and　are　simulated　based　on　65,　45,　and　32　nm　BSIM4　SPICE　models　by　the　HSPICE　tools.　The　simulation　results　show　that　this　technology　is　effective　for　high　performance　and　low　power　operation.　The　power-delay　product　(PDP)　is　reduced　by　up　to　42.37%　compared　to　standard　domino　circuits.　Moreover,　a　novel　method　for　power　distribution　is　introduced.　With　this　method,　taking　a　Zipper　CMOS　full-adder　in　45nm　technology　as　an　example,　the　paths　for　charge　self-compensation　is　optimized　to　minimize　the　power.　Finally,　the　influence　of　W/L　of　nMOS　and　pMOS　in　the　path　for　charge　self-compensation　and　input　of　the　circuits　on　this　technology　is　analyzed　thoroughly.

关键词：

Adders CMOS integrated circuits Delay circuits Fasteners Low power electronics SPICE Timing circuits

作者机构：

[ 1 ] [Wang, Jinhui]VLSI and System Laboratory, Beijing University of Technology, Beijing 100022, China
[ 2 ] [Gong, Na]College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China
[ 3 ] [Hou, Ligang]VLSI and System Laboratory, Beijing University of Technology, Beijing 100022, China
[ 4 ] [Wu, Wuchen]VLSI and System Laboratory, Beijing University of Technology, Beijing 100022, China
[ 5 ] [Dong, Limin]VLSI and System Laboratory, Beijing University of Technology, Beijing 100022, China

通讯作者信息：

电子邮件地址：

wangjinhui888@yahoo.com.cn

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