In　order　to　raise　parallelism　of　executing　instructions　by　model　machine,　this　paper　introduces　the　schema　of　designing　a　pipeline　model　machine.　Using　Verilog　HDL,　a　pipeline　model　machine　with　parallelism　of　instructions　which　is　combined　with　top-down　method　and　deterministic　finite　automation　(DFA)　is　implemented.　The　schema　and　some　algorithms　of　the　pipeline　model　machine　were　described　and　this　machine　was　simulated.　The　simulation　results　show　that　the　model　machine　can　process　4　instructions　at　the　same　time,　and　has　the　performances　of　prefetching　instructions　and　bypassing.