Design and optimization of low-power processor for wireless sensor network - 文章详情页

作者：

Zhao, Gang (Zhao, Gang.) | Hou, Ligang (Hou, Ligang.) | Luo, Rengui (Luo, Rengui.) | Liu, Yuan (Liu, Yuan.) | Wu, Wuchen (Wu, Wuchen.) (学者：吴武臣)

收录：

EI Scopus PKU CSCD

摘要：

A　low　power　processor　(LPP)　for　wireless　sensor　network　(WSN)　is　implemented,　based　on　90nm　technology.　In　order　to　reduce　power　consumption,　two　methods　are　selected　in　the　design.　Clock　gating　technique　is　used　to　reduce　the　dynamic　power　dissipations,　and　multiple　threshold　voltage　library　is　adopted　to　depress　leakage　power　consumption.　This　paper　reports　the　design　results　with　a　brief　discussion.

关键词：

Leakage currents Threshold voltage Optimization Wireless sensor networks

作者机构：

[ 1 ] [Zhao, Gang]Beijing University of Technology, Beijing 100022, China
[ 2 ] [Hou, Ligang]Beijing University of Technology, Beijing 100022, China
[ 3 ] [Luo, Rengui]Beijing University of Technology, Beijing 100022, China
[ 4 ] [Liu, Yuan]Beijing University of Technology, Beijing 100022, China
[ 5 ] [Wu, Wuchen]Beijing University of Technology, Beijing 100022, China

通讯作者信息：

电子邮件地址：

zhaogang1213@emails.bjut.edu.cn

查看成果更多字段

成果类型
所属机构

所有年份指定年份从至