H.264 chip power grid optimization by IO cell placement - 文章详情页

作者：

Hou, Li-Gang (Hou, Li-Gang.) | Li, Mo (Li, Mo.) | Xie, Tong (Xie, Tong.) | Wu, Wu-Chen (Wu, Wu-Chen.) (学者：吴武臣)

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EI Scopus PKU CSCD

摘要：

To　optimize　the　power　grid　design　of　a　H.264　video　decoder　chip,　the　authors　put　forward　the　novel　algorithm　on　an　auto　I/O　cell　placement　(IOAP).　The　corresponding　software　is　developed,　and　the　experiment　is　done.　The　result　of　H.264　video　decoder　chip　is　obvious,　and　7.22%　of　the　total　length　and　16.57%　of　the　routing　time　is　saved.　The　whole　chip＇s　performance　and　design　convergence　has　been　improved.

关键词：

Algorithms Automation Computer aided design Optimization Power supply circuits

作者机构：

[ 1 ] [Hou, Li-Gang]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 2 ] [Li, Mo]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 3 ] [Xie, Tong]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 4 ] [Wu, Wu-Chen]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China

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