Designing leakage-tolerant and noise-immune enhanced low power wide OR dominos in sub-70 nm CMOS technologies - 文章详情页

作者：

Guo, Baozeng (Guo, Baozeng.) | Gong, Na (Gong, Na.) | Wang, Jinhui (Wang, Jinhui.)

收录：

EI Scopus PKU CSCD

摘要：

Two　new　circuit　techniques　to　suppress　leakage　currents　and　enhance　noise　immunity　while　decreasing　the　active　power　are　proposed.　Eight-input　OR　gate　circuits　constructed　with　these　techniques　are　simulated　using　45　nm　BSIM4　SPICE　models　in　HSPICE.　The　simulation　results　show　that　the　proposed　circuits　effectively　lower　the　active　power,　reduce　the　total　leakage　current,　and　enhance　speed　under　similar　noise　immunity　conditions.　The　active　power　of　the　two　proposed　circuits　can　be　reduced　by　up　to　8.8%　and　11.8%　while　enhancing　the　speed　by　9.5%　and　13.7%　as　compared　to　dual　Vt　domino　OR　gates　with　no　gating　stage.　At　the　same　time,　the　total　leakage　currents　are　also　reduced　by　up　to　80.8%　and　82.4%,　respectively.　Based　on　the　simulation　results,　the　state　of　the　evaluation　node　is　also　discussed　to　reduce　the　total　leakage　currents　of　dual　Vt　dominos.

关键词：

CMOS integrated circuits Computer simulation Gates (transistor) Gaussian noise (electronic) Leakage currents

作者机构：

[ 1 ] [Guo, Baozeng]College of Electronic and Information Engineering, Hebei University, Baoding 071002, China
[ 2 ] [Gong, Na]College of Electronic and Information Engineering, Hebei University, Baoding 071002, China
[ 3 ] [Wang, Jinhui]Laboratory of VLSI and Systems, College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing 100022, China

通讯作者信息：

电子邮件地址：

查看成果更多字段

成果类型
所属机构

所有年份指定年份从至