Fractional-N CMOS DPLL with self-calibration - 文章详情页

作者：

Liu, Sujuan (Liu, Sujuan.) | Yang, Weiming (Yang, Weiming.) | Chen, Jianxin (Chen, Jianxin.) | Cai, Liming (Cai, Liming.) | Xu, Dongsheng (Xu, Dongsheng.)

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EI Scopus PKU CSCD

摘要：

A　digital　phase-locked　loop　(DPLL)　based　on　a　new　digital　phase-frequency　detector　is　presented.　The　self-calibration　technique　is　employed　to　acquire　wide　lock　range,　low　jitter,　and　fast　acquisition.　The　DPLL　works　from　60　to　600　MHz　at　a　supply　voltage　of　1.8　V.　It　also　features　a　fractional-N　synthesizer　with　digital　2nd-order　sigma-delta　noise　shaping,　which　can　achieve　a　short　lock　time,　a　high　frequency　resolution,　and　an　improved　phase-noise　spectrum.　The　DPLL　has　been　implemented　in　SMIC　0.18　μm　1.8　V　1P6M　CMOS　technology.　The　peak-to-peak　jitter　is　less　than　0.8%　of　the　output　clock　period　and　the　lock　time　is　less　than　150　times　of　the　reference　clock　period　after　the　pre-divider.

关键词：

Jitter Oscillators (electronic) CMOS integrated circuits Calibration Phase locked loops

作者机构：

[ 1 ] [Liu, Sujuan]Optoelectronics Laboratory, Beijing University of Technology, Beijing 100022, China
[ 2 ] [Yang, Weiming]Optoelectronics Laboratory, Beijing University of Technology, Beijing 100022, China
[ 3 ] [Chen, Jianxin]Optoelectronics Laboratory, Beijing University of Technology, Beijing 100022, China
[ 4 ] [Cai, Liming]China Integrated Circuit Design Center, Beijing 100015, China
[ 5 ] [Xu, Dongsheng]China Integrated Circuit Design Center, Beijing 100015, China

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